Publications

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2012

• CHEVILLON N., SALLESE J.-M., LALLEMENT C., PRÉGALDINY F., MADEC M., SEDLMEIR J. and AGHASSI J.

Generalization of the Concept of Equivalent Thickness and Capacitance to Multigate MOSFETs Modeling

IEEE Transaction on Electron Devices, vol. 59, N° 1, pages 60-71, 2012 Lien

• HEITZ J., DUMAS N., FRICK V., LALLEMENT C., HÉBRARD L.,

Modeling and optimization of a Ker charge pump loaded by a resistive circuit,

19th IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'2012), Warsaw (Poland), May 24-26, 2012, Proc. pp. 376-381. Lien

• MADEC M., SCHELL J.B., KAMMERER J.B., LALLEMENT C., HÉBRARD L.,

Compact modeling of vertical Hall-effect devices: Electrical behavior,

10th IEEE International NEWCAS Conference (NEWCAS 2012), Montreal (Canada), June 17-20, 2012, Proc. pp. 213-216. Lien

2011

• GENDRAULT Y., MADEC M., LALLEMENT C., PÊCHEUX F., HAIECH J.,

Synthetic biology methodology and model refinement based on microelectronic modeling tools and languages

Biotechnologies Journal, vol. 6, pp. 796-806, 2011. Lien

• HEITZ J., LEROY Y., HÉBRARD L., LALLEMENT C.,

Theoretical characterization of the topology of connected carbon nanotubes in random networks,

Nanotechnology 22, 345703, pages 1-7, 2011. Lien

• SALLESE J.-M., CHEVILLON N., LALLEMENT C., IÑIGUEZ B., PRÉGALDINY F.,

Charge Based Modelling of Junctionless Double Gate Field-Effect Transistors,

IEEE Transactions on Electron Devices,vol. 58, pages 2628-2637, août 2011.Lien

• YESAYAN A., PRÉGALDINY F., CHEVILLON N., LALLEMENT C., SALLESE J.-M.,

Physics-based compact model for ultra-scaled finFETs,

Solid-State Electronics, vol. 62, pages 165-173, août 2011.Lien

• SALLESE J.M., PRÉGALDINY F., LALLEMENT C.

Double-gate MOSFETs for SOI technologies

Nano-Tera Workshop on the Next Generation MOSFET Compact Models, Lausanne (Switzerland), December 15-16, 2011. Lien

2010

• SALLESE J.M., CHEVILLON N., PRÉGALDINY F., LALLEMENT C., IÑIGUEZ B.,

The equivalent-thickness concept for doped symmetric DG MOSFETs,

IEEE Transactions on Electron Devices 57, 2010, pp. 2917-2924. Lien.

• GENDRAULT Y., MADEC M., LALLEMENT C., HAIECH J.,

A design kit for synthetic biology,

International Conference on Synthetic Biology, Evry (France), December 15-16, 2010.

• GENDRAULT Y., MADEC M., LALLEMENT C., HAIECH J.,

Multi-abstraction modeling in synthetic biology,

3rd IEEE International Symposium on Applied Sciences in Biomedical and Communication Technologies (ISABEL 2010), Rome (Italy), November 7-10, 2010, Proc. pp. 1-5. Lien

• MADEC M., GENDRAULT Y., LALLEMENT C., HAIECH J.,

Design methodology and modeling for synthetic biosystems,

Int. J. Microelectron. Comput. Sci. 1, 2010, pp. 147-155.

• MADEC M., LALLEMENT C., GENDRAULT Y., HAIECH J.,

La microélectronique et la biologie synthétique,

Conference Savoir en commun "Le Corps", Strasbourg (France), November 18, 2010. Lien

• MADEC M., LALLEMENT C., GENDRAULT Y., HAIECH J.,

Design methodology for synthetic biosystems,

17th IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'2010), Wrocaw (Poland), June 24-26, 2010, Proc. pp. 621-626. Lien

• PÊCHEUX F., MADEC M., LALLEMENT C.,

Is SystemC-AMS an appropriate "promoter" for the modeling and simulation of bio-compatible systems?,

IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris (France), May 30 - June 2, 2010, Proc. pp. 1791-1794. Lien

• YESAYAN A., CHEVILLON N., PRÉGALDINY F., LALLEMENT C.,

Compact physics-based model for ultrashort FinFETs,

17th IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'2010), Wroclaw (Poland), June 24-26, 2010, Proc. pp. 75-80. Lien

2009

• TANG M., PRÉGALDINY F., LALLEMENT C., SALLESE J.M.,

Explicit compact model for ultranarrow body FinFETs,

IEEE Transactions on Electron Devices 56, 2009, pp. 1543-1547. Lien.

• CHEVILLON N., TANG M., PRÉGALDINY F., MADEC M., LALLEMENT C.,

Modèle compact de FinFET et extraction de paramètres,

Journées-atelier des Groupement de Recherche SiP SoC et Nanoélectronique, Bordeaux (France), December 9-11, 2009.

• CHEVILLON N., TANG M., PRÉGALDINY F., LALLEMENT C., MADEC M.,

FinFET compact modeling and parameter extraction,

16th IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'2009), Lodz (Poland), June 25-27, 2009, Proc. pp. 55-60, papier invité. Lien

• LALLEMENT C.,

Modélisation compacte FINFET,

Journées-atelier des Groupement de Recherche SiP SoC et Nanoélectronique, Bordeaux (France), December 9-11, 2009, papier invité.

• MADEC M., LALLEMENT C., KARSTENS K., DITTMAN S., GERSBACHER M., SORG R., WILD M., MULLER M., BOURGINE P., DONZEAU M., HAIECH J.,

Synthetic biology and microelectronics: A similar design flow,

Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA'09), Toulouse (France), June 28 - July 1, 2009, Proc. pp. 1-4. Lien

• TANG M., PRÉGALDINY F., LALLEMENT C., SALLESE J.M.,

Quantum compact model for ultra-narrow body FinFET,

10th IEEE International Conference on ULtimate Integration of Silicon (ULIS09), Aachen (Germany), March 18-20, 2009, Proc. pp. 293-296. Lien

• TANG M., PRÉGALDINY F., LALLEMENT C.,

Quantum compact model for ultra-short and ultra-narrow body FinFET,

MOS-AK Meeting of the MOS Modeling and Parameter Extraction Group, Frankfurt /Oder (Germany), April 2-3, 2009. Lien

• TANG M., PRÉGALDINY F., LALLEMENT C.,

Compact modeling of both n- and p-type ultra-short FinFETs,

Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA'09), Toulouse (France), June 28 - July 1, 2009, Proc. pp. 1-4. Lien

2008

• DIAGNE B., PRÉGALDINY F., LALLEMENT C., SALLESE J.M., KRUMMENACHER F.,

Explicit compact model for symmetric double-gate MOSFETs including solutions for small-geometry effects,

Solid-State Electronics 52, 2008, pp. 99-106. Lien.

• MADEC M., KAMMERER J.B., PRÉGALDINY F., HÉBRARD L., LALLEMENT C.,

Compact modeling of magnetic tunnel junction,

Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA'08), Montréal (Canada), June 22-25, 2008, Proc. pp. 229-232. Lien

2007

• O’CONNOR I., LIU J., GAFFIOT F., PRÉGALDINY F., LALLEMENT C., MANEUX C., GOGUET J., FRÉGONÈSE S., ZIMMER T., ANGHEL L., DANG T., LEVEUGLE R.,

CNTFET Modeling and Reconfigurable Logic Circuit Design,

IEEE Transactions on Circuits and Systems - I: Regular papers, vol. 54, n°11, pages 2365 - 2379, novembre 2007. Lien

• GRABINSKI W., GRASSER T., GILDENBLAT G., SMIT G., BUCHER M., AARTS A.C.T., TAJIC A., CHAUHAN Y.S., NAPIERALSKI A., FJELDLY T.A., IÑIGUEZ B., IANNACCONE G., KAYAL M., POSCH W., WACHUTKA G., PRÉGALDINY F., LALLEMENT C., LEMAITRE L.,

MOS-AK: Open compact modeling forum,

4th International Workshop on Compact Modeling (IWCM 2007), Yokohama (Japan), January 23, 2007, papier invité. Lien

2006

• PRÉGALDINY F., LALLEMENT C., DIAGNE B., SALLESE J.M., KRUMMENACHER F.,

Compact modeling of emerging technologies with VHDL-AMS,

Advances in Design and Specification Languages for Embedded Systems, 2007, pp. 5-21, Forum on specification & Design Languages (FDL'06), Darmstadt (Germany), September 19-22, 2006, Proc. pp. 23-30, edited by S.A. Huss, Springer, ISBN 978-1-4020-6147-9. Lien

• DIAGNE B., PRÉGALDINY F., LALLEMENT C., SALLESE J.M., KRUMMENACHER F.,

Modèle compact de DG MOSFET dédié à la conception de circuits,

7ème Colloque sur le Traitement Analogique de l'Information, du Signal et ses Applications (TAISA'2006), Strasbourg (France), October 19-20, 2006, Actes pp. 105-108.

• DIAGNE B., PRÉGALDINY F., LALLEMENT C.,

Modèle compact de transistor MOS double-grille pour la simulation de circuits,

IXèmes Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM'2006), Rennes (France), May 10-12, 2006.

• LALLEMENT C., PÊCHEUX F., VACHOUX A., PRÉGALDINY F.,

Compact modeling of the MOSFET in VHDL-AMS,

Transistor level modeling for analog/RF IC design, 2006, pp. 243-269, edited by W. Grabinski, B. Nauwelaers, D. Schreurs, Springer Verlag, ISBN 1-4020-4555-7. Lien

• PRÉGALDINY F., KRUMMENACHER F., SALLESE J.M., DIAGNE B., LALLEMENT C.,

An explicit quasi-static charge-based compact model for symmetric DG MOSFET,

Workshop on Compact Modeling, NSTI Nanotech 2006, Boston (USA), May 7-11, 2006, Proc. pp. 686-691, ISBN 0-9767985-8-1, papier invité. Lien

• PRÉGALDINY F., KRUMMENACHER F., DIAGNE B., PÊCHEUX F., SALLESE J.M., LALLEMENT C.,

Explicit modelling of the double-gate MOSFET with VHDL-AMS,

Int. J. Numer. Model.: Electron. Netw. Devices Fields 19, 2006, pp. 239-256. Lien.

• PRÉGALDINY F., LALLEMENT C., KAMMERER J.B.,

Design-oriented compact models for CNTFETs,

1st IEEE International Conference on Design & Test of Integrated Systems in nanoscale technology (DTIS 06), Tunis (Tunisia), September 5-7, 2006, Proc. pp. 34-39, papier invité. Lien

• PRÉGALDINY F., KAMMERER J.B., LALLEMENT C.,

Compact modeling and applications of CNTFETs for analog and digital circuit design,

13th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2006), Nice (France), December 10-13, 2006, Proc. pp. 1030-1033. Lien

2005

• PÊCHEUX F., LALLEMENT C., VACHOUX A.

VHDL-AMS and Verilog-AMS as alternative HDL's for the Efficient Modeling of Multi-disciplines Schemes,

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, n°2, pages 204-225, février 2005. Lien

• SALLESE J.-M., KRUMMENACHER F., PRÉGALDINY F., LALLEMENT C., ROY A., ENZ C.,

A design oriented current model for DG MOSFET and its correlation with the EKV formalism,

Solid-State Electronics, vol. 49 pages 485-489, mars 2005. Lien

• DIAGNE B., PRÉGALDINY F., KRUMMENACHER F., PÊCHEUX F., SALLESE J.M., LALLEMENT C.,

Design oriented model for symmetrical DG-MOSGET,

MOS-AK Meeting, Strasbourg (France), April 8, 2005. Lien

• PÊCHEUX F., ALLARD B., LALLEMENT C., VACHOUX A., MOREL H.,

Modeling and simulation of multi-discipline systems using bond graphs and VHDL-AMS,

International Conference on Bond Graph Modeling and Simulation (ICBGM'2005), New Orleans (USA), January 23-27, 2005. Lien

• PRÉGALDINY F., LALLEMENT C.,

Fourth generation MOSFET model and its VHDL-AMS implementation,

Int. J. Numer. Model.: Electron. Netw. Devices Fields 18, 2005, pp. 39-48. Lien.

• PRÉGALDINY F., KRUMMENACHER F., DIAGNE B., ROY A., SALLESE J.M., LALLEMENT C.,

A closed-form compact model for symmetric Double-Gate (DG) MOSFETs,

MOS-AK Workshop, Grenoble (France), September 16, 2005. Lien

2004

• PRÉGALDINY F., LALLEMENT C., MATHIOT D.,

Accounting for quantum mechanical effects from accumulation to inversion, in a fully analytical surface-potential-based MOSFET model,

Solid-State Electronics, vol. 48, n° 5, pages 781-787, mai 2004. Lien

• BUCHER M., LALLEMENT C., KRUMMENACHER F., ENZ C.,

A MOS transistor model for mixed analog-digital circuit design and simulation,

Design of system on a chip: Devices & components, 2004, pp. 49-96, edited by R. Reis, J. Jess, Kluwer Academic Publishers, ISBN 1-4020-7928-1.

• LALLEMENT C., PÊCHEUX F., GRABINSKI W.,

High level description of thermodynamical effects in the EKV 2.6 MOST model,

EKV 2.6 Users' Meeting, Lausanne (Switzerland), November 4, 2004, papier invité. Lien

• PRÉGALDINY F., LALLEMENT C.,

Fourth generation MOSFET model and its VHDL-AMS implementation,

MOS Modeling and Parameter Extraction Group Meeting, Stuttgart (Germany), May 7, 2004, papier invité. Lien

• SALLESE J.M., ROY A., KRUMMENACHER F., PRÉGALDINY F., LALLEMENT C., ENZ C.,

A design oriented current model for symmetrical DG MOSFET: Correlation with the EKV formalism, EKV 3.0,

Workshop, Lausanne (Switzerland), November 5, 2004, papier invité.

2003

• LALLEMENT C., SALLESE J.M., BUCHER M., GRABINSKI W., FAZAN P.C.,

Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model,

IEEE Transactions on Electron Devices 50, 2003, pp. 406-417. Lien.

• PÊCHEUX F., LALLEMENT C.,

VHDL-AMS and Verilog-AMS as competitive solutions,

System Specification and Design Languages, 2003, pp. 41-43, 5th Forum on Specification and Design Languages (FDL'02), Marseille (France), September 24-27, 2002, edited by E. Villar, J.P. Mermet, Kluwer Academic Publishers, ISBN 978-1-4020-7414-1. Lien

• PRÉGALDINY F., LALLEMENT C., MATHIOT D.,

Modélisation analytique avancée des capacités parasites du transistor MOS fortement submicronique,

VIèmes Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM'2003), Toulouse (France), May 14-16, 2003, Actes pp. 311-313. Lien

• PRÉGALDINY F., LALLEMENT C., GRABINSKI W., KAMMERER J.B., MATHIOT D.,

An analytical quantum model for the surface potential of deep-submicron MOSFETs,

10th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'2003), Lodz (Poland), June 26-28, 2003, Proc. pp. 98-104, papier invité.

• PRÉGALDINY F., LALLEMENT C., MATHIOT D.,

Quantum surface potential model suitable for advanced MOSFETs simulation,

IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'03), Boston (USA), September 3-5, 2003, Proc. pp. 227-230. Lien

2002

• PRÉGALDINY F., LALLEMENT C., MATHIOT D.,

A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs,

Solid-State Electronics, vol. 46, pages 2191-2198, décembre 2002. Lien

• BUCHER M., ENZ C., KRUMMENACHER F., SALLESE J.M., LALLEMENT C., PORRET A.S.,

The EKV compact MOS transistor model: Accounting for deep-submicron aspects,

5th International Conference on Modeling and Simulation of Microsystems (MSM 2002), San Juan (USA), April 22-25, 2002, Proc. pp. 670-673, ISBN 0-9708275-7-1, papier invité. Lien

• BUCHER M., SALLESE J.M., KRUMMENACHER F., KAZAZIS D., LALLEMENT C., GRABINSKI W., ENZ C.,

EKV 3.0: An analog design-oriented MOS transistor model,

9th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'2002), Wroclaw (Poland), June 20-22, 2002, Proc. pp. 51-54, papier invité.

• LALLEMENT C., PÊCHEUX F., HERVÉ Y.,

VHDL-AMS case study: The incremental design of an efficient 3rd generation MOS model of deep sub micron transistor,

SOC Design Methodologies, 2002, pp. 467-472, 11th International Conference on Very Large Scale Integration of Systems-on-Chip (IFIP VLSI-SOC 2001), Montpellier (France), December 3-5, 2001, edited by M. Robert, B. Rouzeyre, C. Piguet, M.L. Flottes, Kluwer Academic Publishers, ISBN 1-4020-7148-5. Lien

• LALLEMENT C., PÊCHEUX F., GRABINSKI W.,

High level description of thermodynamical effects in the EKV 2.6 MOST model,

9th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'2002), Wroclaw (Poland), June 20-22, 2002, Proc. pp. 45-50, papier invité.

• PRÉGALDINY F., LALLEMENT C., MATHIOT D.,

Extrinsic capacitance model for advanced MOSFET design,

MOS Modeling and Parameter Extraction Group Meeting, Erfurt (Germany), October 21, 2002. Lien

2001

• BUCHER M., SALLESE J.M., LALLEMENT C.,

Accounting for quantum effects and polysilicon depletion in an analytical design-oriented MOSFET model,

International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 01), Athens (Greece), September 5-7, 2001, Proc. pp. 296-299, edited by D. Tsoukalas, C. Tsamis, Springer Verlag, Vienna, New York, ISBN 3-211-83708-6.

• LALLEMENT C., PÊCHEUX F., HERVÉ Y.,

VHDL-AMS design of a MOST model including deep submicron and thermal-electronic effects,

5th IEEE International Workshop on Behavioral Modeling and Simulation (BMAS 2001), Santa Rosa (USA), October 10-12, 2001, Proc. pp. 91-96, ISBN 0-7803-7291-3. Lien

• SALLESE J.M., GRABINSKI W., PORRET A.S., BUCHER M., LALLEMENT C., KRUMMENACHER F., ENZ C., FAZAN P.,

Advancements in DC and RF MOSFET modelling with the EPFL-EKV charge based model,

8th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'2001), Zakopane (Poland), June 21-23, 2001, Proc. pp. 45-52, edited by A. Napieralski, Tech. Univ. Lodz.

2000

• SALLESE J.M., BUCHER M., LALLEMENT C.,

Improved analytical modelling of polysilicon depletion in MOSFETs for circuit simulation,

Solid-State Electronics 44, 2000, pp. 905-912. Lien.

• SALLESE J.M., BUCHER M., LALLEMENT C., GRABINSKI W.,

Advances in AC modelling of MOSFET using EKV formalism,

Silicon RF-IC: Modeling and Simulation Workshop, Lausanne (Switzerland), February 24-25, 2000.